Field of the Invention
The invention relates to a circuit configuration for a multistandard communications terminal that includes a radio frequency component for receiving RF-input signals of different system standards. The radio-frequency component includes a conversion stage for down-converting a received RF-input signal into a received analog signal. The multistandard communications terminal has a digital-signal processing circuit for converting the analog signal into a digital signal. The digital-signal processing circuit has a digital filter that receives the digital signal and therefrom outputs a band-limited digital output signal. The digital filter has a pass-band that is adjustable.
In current conventional communications systems, particularly in those which implement wireless communication, analog signals of a predefined bandwidth B are received. This bandwidth B is system-specific. For example, the bandwidth B of signals in the Global System for Mobile Communications (GSM) is 200 kHz and the bandwidth in the CDMA (Code Division Multiple Access) system IS-95 is 1.25 MHz.
Multistandard terminals (also referred to as multiband devices), which support a plurality of system standards, for example both GSM and IS-95, are already known. These devices use a dedicated standard-specific analog-digital (A/D) converter for each system standard, to which a correspondingly optimized, similarly standard-specific selection filter is connected in the digital domain. The A/D converters separately digitize signals with a bandwidth Bxe2x80x2 which is greater than the bandwidth B. The selection filters perform the bandwidth limitation to the respectively required standard-specific bandwidth B and decimate the sampling rate (sampling reduction). Each combination of an A/D converter and a selection filter is predefined.
In these known communications terminals, it is disadvantageous that the use of standard-specific A/D transformers and corresponding standard-specific selection filters represents a relatively substantial hardware outlay. A further disadvantage of these devices is that the subsequent incorporation of further system standards can normally be implemented only by means of hardware modifications.
U.S. Pat. Nos. 5,619,536 and 5,557,642 in each case describe receiver circuits for mobile radio communications which have a radio-frequency component, a receiver conversion stage, a signal-processing circuit, an A/D converter, a selection unit and a digital filter. The digital filter has a variable bandwidth which can be set according to the system standard which is used.
International Publication WO 87 01531 A discloses a digital radio-frequency receiver in which, inter alia, different configurations and combinations of digital filters are described.
It is accordingly an object of the invention to provide a circuit configuration for a multistandard communications terminal which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide a circuit configuration for a multistandard communications terminal that can be implemented with little hardware outlay and that offers high flexibility in terms of the system standards which can be received with the multistandard communications terminal.
With the foregoing and other objects in view there is provided, in accordance with the invention a circuit configuration for a multistandard communications terminal, in which the circuit configuration includes a radio frequency component for receiving RF input signals of different system standards and a signal processing circuit. The radio frequency component includes a receiver conversion stage for converting an RF receive signal into an analog receive signal through down-conversion using a predefined conversion frequency. The RF receive signal is formed from at least one of the received RF input signals. The signal-processing circuit includes an A/D converter for converting the analog receive signal into a digital receive signal. The signal-processing circuit includes a selection unit having a digital filter that receives the digital receive signal and outputs a bandwidth-limited digital output signal. The digital filter has a variably adjustable pass-band in which the pass-band is set according to a required one of the different system standards. The digital filter includes a programmable read-only memory storing a table that allocates a set of filter coefficients to each one of the different system standards.
Due to the variability of the pass-band of the digital filter, a standard-specific band limitation can be performed therewith, the same digital filter being used for the bandwidth limitation of all received system standards. The hardware outlay is thus reduced, since it is no longer necessary to provide a digital filter which is separately designed for each system standard.
In addition, the incorporation of subsequently emerging system standards is also enabled by means of a suitable programming functionality of the filter. The flexibility and functional range of the multistandard communications terminal is thereby further increased.
A required system standard can, on the one hand, be defined automatically in that the circuit configuration recognizes a received system standard by evaluating the corresponding RF input signals, in particular radio signals, and by subsequently setting the pass-band of the digital filter according to the recognized system standard. In the case of locally changing system standards, it is then always ensured that the multistandard communications terminal is set to the local system standard. On the other hand, it is also possible for the selection of the system standard to be made by the subscriber himself. This enables the subscriber to select specifically between different standards, for example GSM and IS-95, insofar as radio signals of a plurality of system standards are present. Since different system standards are also normally based on different networks and different network operators, the subscriber is thus also able to choose between the different user facilities of the networks and service offerings and services of the network operators.
The term xe2x80x9csystem standardxe2x80x9d used here is to be understood in a broad sense. Different system standards according to the definition used here occur (at least) whenever the systems use RF input signals (radio signals) of different bandwidths.
The analog received signal generated through downconversion may involve both a baseband signal and a signal in an intermediate frequency range (for example 300 MHz in GSM). In other words, the invention includes not only circuit configurations for xe2x80x9cdirect conversion receiversxe2x80x9d operating according to the homodyne principle but also circuit configurations for heterodyne receivers.
In accordance with an added feature of the invention, the selection unit furthermore preferably includes a sampling rate reduction circuit with a variable sampling rate reduction. The sampling rate reduction that is set in operation is determined by the required system standard. In addition to the standard-specific band limitation, a standard-specific reduction of the sampling rate is also effected by this measure. The sampling rate present at the output of the selection unit can thereby be set in such a way that it meets the different requirements of the individual system standards in terms of symbol rate and signal dynamic range.
The digital filter can be structurally implemented in different ways.
In accordance with an additional feature of the invention, in a first embodiment, the digital filter is designed in the form of an integrated circuit with a coefficient input for setting filter coefficients. The filter is then (system-standard-specifically) configured by entering filter coefficients allocated to a specific system standard. The integrated circuit may contain a shift register connected to the coefficient input to store the filter coefficients.
In accordance with another feature of the invention, in a second embodiment, the digital filter includes a programmable read-only memory (EEPROM), in which a table is stored that allocates a set of filter coefficients to each system standard. In this case, the required filter coefficients are already contained in the digital filter chip and only the required coefficient set must be retrieved by means of an externally performed selection. In this variant, it is advantageous that the digital filter can be adapted to new system standards by re-programming the read-only memory (i.e. by storing new coefficient sets).
In accordance with a further feature of the invention, in order to carry out the calculation operation representing the filtering, the filter may include hard-wired digital circuits such as an adder, a multiplier, a shift register and the like. The actual circuit design defines the filter type (for example, serial, parallel, FIR, IIR). In a different option, the digital filter is designed as a programmable signal processor. In this case, the filter type used is initially variable, and is only defined by the signal processor programming.
In accordance with a further added feature of the invention, both FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) digital filters can be used. Whereas IIR filters have a higher selectivity and a lower calculation requirement than FIR filters, the latter have the advantage, inter alia, that, independently of the coefficient selection, they always have a very low tendency towards oscillation, i.e. they have equally good stability characteristics for all system standards.
In accordance with a further additional feature of the invention, a favorable implementation of the digital filter from the point of view of minimum calculation outlay is provided. This implementation is characterized in that the digital filter includes a plurality of individual filters, the sampling rate reduction circuit includes a plurality of individual sampling rate reduction circuits, and the individual filters and the individual sampling rate reduction circuits are configured alternately in series.
In accordance with yet an added feature of the invention, in order to increase conversion accuracy, a delta-sigma (xcex94xcexa3) A/D converter, particularly a third-order converter, is preferably used. Substantial quantization error reduction and therefore an improvement in the signal-to-noise ratio at the output of the selection unit can thereby be achieved.
In accordance with yet an additional feature of the invention, the delta-sigma A/D converter is operated at a sampling rate according to the selected one of the different system standards.
In accordance with a concomitant feature of the invention, the digital filter preferably has an order between 5 and 20, and even more preferably, the digital filter has an order between 10 and 18.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for a multistandard communications terminal, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.